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Johansson, B., Leander, B., Holmgren, O., Nolte, T. & Papadopoulos, A. (2026). Checkpointing and State Transfer for Industrial Controller Redundancy. Journal of systems architecture, 178, 103872
Open this publication in new window or tab >>Checkpointing and State Transfer for Industrial Controller Redundancy
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2026 (English)In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 178, p. 103872-Article in journal (Refereed) Published
Abstract [en]

Industrial controllers are moving from controller-centric to network-centric architectures, where lightweight containerization is increasingly adopted in operational technology. Many industrial domains require high reliability, often achieved through spatial standby redundancy with duplicated controllers where one is the active primary and the other a standby backup. In such setups, the standby backup must seamlessly take over control when the primary fails. Hence, the backup needs to be up-to-date with respect to the primary's internal state. The retrieval of internal states is commonly known as checkpointing. We review checkpointing approaches used in virtualized and industrial settings and derive a set of desired features for state-transfer protocols. We then assess existing communication protocols against these features and experimentally evaluate the two strongest contenders under no-loss and packet-loss conditions, measuring recovery performance. The analysis reveals that none of the protocols assessed meets all the desired features. To address this gap, we introduce a new state-transfer protocol that satisfies all identified features. In experiments, it demonstrates good performance under packet loss, with only a slight reduction in throughput compared to the identified top contender protocols that we used for comparison. 

Place, publisher, year, edition, pages
Elsevier BV, 2026
Keywords
Checkpointing, Communication, Fault tolerance, Industrial control systems, Redundancy, Reliability, State transfer
National Category
Computer Systems Embedded Systems
Identifiers
urn:nbn:se:mdh:diva-73188 (URN)10.1016/j.sysarc.2026.103872 (DOI)001796351400001 ()2-s2.0-105041450224 (Scopus ID)
Available from: 2025-09-05 Created: 2025-09-05 Last updated: 2026-07-01Bibliographically approved
Fiaschi, G., Vitucci, C., Westerback, T., Sundmark, D. & Nolte, T. (2025). A Formal Model for Path Set Attribute Calculation in Network Systems. In: 2025 International Symposium on Networks, Computers and Communications (ISNCC): . Paper presented at 2025 International Symposium on Networks, Computers and Communications (ISNCC) (pp. 1-8). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>A Formal Model for Path Set Attribute Calculation in Network Systems
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2025 (English)In: 2025 International Symposium on Networks, Computers and Communications (ISNCC), Institute of Electrical and Electronics Engineers (IEEE) , 2025, p. 1-8Conference paper, Published paper (Refereed)
Abstract [en]

In graph theory and its practical networking applications, e.g., telecommunications and transportation, the problem of finding paths has particular importance. Selecting paths requires giving scores to the alternative solutions to drive a choice. While previous studies have provided comprehensive evaluation of single-path solutions, the same level of detail is lacking when considering sets of paths. This paper emphasizes that the path characterization strongly depends on the properties under consideration. While property-based characterization is also valid for single paths, it becomes crucial to analyse multiple path sets. From the above consideration, this paper proposes a mathematical approach, defining a functional model that lends itself well to characterizing the path set in its general formulation. The paper shows how the functional model contextualizes specific attributes.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2025
Series
International Symposium on Networks, Computers and Communications, ISSN 2768-0940
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:mdh:diva-74717 (URN)10.1109/isncc66965.2025.11250449 (DOI)2-s2.0-105031405278 (Scopus ID)978-1-6654-5769-9 (ISBN)
Conference
2025 International Symposium on Networks, Computers and Communications (ISNCC)
Funder
Knowledge Foundation
Available from: 2025-12-02 Created: 2025-12-02 Last updated: 2026-03-11Bibliographically approved
Itani, W., Shamseddine, M., Al-Dulaimy, A., Nolte, T. & Papadopoulos, A. (2025). DCGUARD: A Holistic Approach for Detecting and Isolating Malicious Nodes in Cloud Data Centers. IEEE Transactions on Dependable and Secure Computing, 22(4), 4248-4265
Open this publication in new window or tab >>DCGUARD: A Holistic Approach for Detecting and Isolating Malicious Nodes in Cloud Data Centers
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2025 (English)In: IEEE Transactions on Dependable and Secure Computing, ISSN 1545-5971, E-ISSN 1941-0018, Vol. 22, no 4, p. 4248-4265Article in journal (Refereed) Published
Abstract [en]

This paper presents DCGUARD, a unified security approach for detecting and isolating misbehaving computing and forwarding nodes in multi-tenant virtualized cloud data centers. DCGUARD employs technological advancements in Virtual Machine Introspection (VMI), Software-Defined Networking (SDN), and secure probabilistic sketching to detect and isolate parts of the Virtual Machines (VMs) and network switches experiencing malicious behavior dynamically. The main contribution lies in designing a divide-and-conquer strategy that utilizes VMI and network programmability to apply focused distributed task and packet probing mechanisms on portions of the data center network rather than focusing the security functions on the entire physical network. The processing VMs and network switches are recursively partitioned into independent logical groups inspected individually to localize abnormal/malicious computing and switching nodes incrementally. This remarkably enhances the efficiency of the detection mechanisms, which opportunistically approaches a logarithmic time complexity in the number of protocol steps towards convergence (compared to a linear time complexity in traditional intrusion detection systems) when a relatively low number of hostile VMs and switches are present. Real experiments are evaluated, and a test-bed blueprint of the proposed design is emulated in a virtualized cloud environment using the Mininet emulator. The performance, convergence, and accuracy benchmarks corroborate the analytical advantage of the proposed security approach.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2025
Keywords
Cloud computing, Data center, SDN, Security, Software-Defined Networking, Virtual machine introspection, VMI
National Category
Computer Sciences
Identifiers
urn:nbn:se:mdh:diva-70417 (URN)10.1109/TDSC.2025.3545338 (DOI)001527227300028 ()2-s2.0-85218895591 (Scopus ID)
Available from: 2025-03-12 Created: 2025-03-12 Last updated: 2025-10-10Bibliographically approved
Vitucci, C., Sundmark, D., Jagemar, M. & Nolte, T. (2025). Fault Management Cost System Analysis in Radio Access Network Embedded Systems. In: 2025 9th International Conference on System Reliability and Safety, ICSRS 2025: . Paper presented at 9th International Conference on System Reliability and Safety, ICSRS 2025, 26-28 November, 2025, Turin, Italy (pp. 477-484). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Fault Management Cost System Analysis in Radio Access Network Embedded Systems
2025 (English)In: 2025 9th International Conference on System Reliability and Safety, ICSRS 2025, Institute of Electrical and Electronics Engineers (IEEE) , 2025, p. 477-484Conference paper, Published paper (Refereed)
Abstract [en]

There is a widely held belief that implementing fault management always costs less than handling faults in the field. However, the relationship between the costs of fault management and maintenance is more complex, and formal decision-making support is often lacking. This paper proposes quantitative methods to evaluate the economic sustainability of fault management solutions and the quality levels that support a product's business case. It introduces a mathematical model describing how investments in fault management reduce expected maintenance costs, and a second model linking the product's fault coverage to its return rate, which reflects both product reliability and potential impacts on brand reputation. Together, these models provide a framework to guide decisions on fault management investment and to quantify the trade-off between implementation cost, operational cost, and product quality.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2025
Keywords
Cost Analysis, Embedded Systems, Fault Management, Telecommunication, Cost accounting, Decision making, Economic and social effects, Economics, Investments, Cost systems, Decision making support, Economic sustainability, Embedded-system, Management costs, Quality levels, Quantitative method, Radio access networks, Cost benefit analysis
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-77541 (URN)10.1109/ICSRS68021.2025.11422109 (DOI)2-s2.0-105036282542 (Scopus ID)9798331549527 (ISBN)
Conference
9th International Conference on System Reliability and Safety, ICSRS 2025, 26-28 November, 2025, Turin, Italy
Available from: 2026-06-11 Created: 2026-06-11 Last updated: 2026-06-29Bibliographically approved
Vitucci, C., Sundmark, D., Jagema, M. & Nolte, T. (2025). Low-level Anomaly Detection in Embedded Systems Using Machine Learning. In: Int. Conf. Comput. Technol. Appl., ICCTA: . Paper presented at 11th International Conference on Computer Technology Applications, ICCTA 2025 (pp. 115-121). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Low-level Anomaly Detection in Embedded Systems Using Machine Learning
2025 (English)In: Int. Conf. Comput. Technol. Appl., ICCTA, Institute of Electrical and Electronics Engineers (IEEE) , 2025, p. 115-121Conference paper, Published paper (Refereed)
Abstract [en]

Let us consider an embedded system as a specific combination of hardware and software that is capable of consistently providing a certain service. Depending on the boundary conditions of the system, such as the working environment and the number of users served, we can say that the statistical distribution of resource usage is a characterization of the embedded system itself and its footprint. The consequence of this distinguishable footprint for embedded systems is that it becomes possible to use the statistical deviation of the resource usage distribution to identify anomalies. In this paper, we will analyze which Performance Metric Unit counters (e.g., CPU usage, memory usage) and resource profiles (e.g., system logs, performance metrics) are most characteristic for detecting a lowlevel anomaly: an alteration of the firmware working cycle or the propagation of a hardware error in the system. We will do this by using baseband products for radio access networks. We will demonstrate that using a machine learning model makes it possible to distinguish both the firmware cycle alteration and the hardware error reporting with an accuracy of more than 99% on unseen and new dataset.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2025
Keywords
Anomaly Detection, Embedded System, Fault Detection, Machine Learning, Embedded software, Embedded systems, Firmware, Learning systems, Condition, Embedded-system, Faults detection, Hardware and software, Hardware error, Machine-learning, Performance metrices, Resource usage, Working environment
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:mdh:diva-74013 (URN)10.1109/ICCTA65425.2025.11166151 (DOI)2-s2.0-105018470209 (Scopus ID)9798331512651 (ISBN)
Conference
11th International Conference on Computer Technology Applications, ICCTA 2025
Available from: 2025-11-03 Created: 2025-11-03 Last updated: 2025-11-03Bibliographically approved
Friebe, A., Cucinotta, T., Marković, F., Papadopoulos, A. & Nolte, T. (2025). Nip It In the Bud: Job Acceptance Multi-Server. In: 2025 IEEE 31st Real-Time and Embedded Technology and Applications Symposium (RTAS): . Paper presented at 2025 IEEE 31st Real-Time and Embedded Technology and Applications Symposium (RTAS),Irvine, CA, USA, 6-9 May 2025 (pp. 26-39). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Nip It In the Bud: Job Acceptance Multi-Server
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2025 (English)In: 2025 IEEE 31st Real-Time and Embedded Technology and Applications Symposium (RTAS), Institute of Electrical and Electronics Engineers (IEEE) , 2025, p. 26-39Conference paper, Published paper (Other academic)
Abstract [en]

Computationally demanding tasks with highly variable execution times may require parallel processing. Scheduling such tasks with low deadline miss rates but without significant overprovisioning is challenging. This issue arises in applications like nonlinear optimization for Model Predictive Control (MPC). The Constant Bandwidth Server (CBS) provides timing isolation, supporting both hard and soft real-time tasks. However, scheduling parallel, time-varying jobs across multiple CBS instances requires static job-to-server assignments, which can lead to resource underutilization due to queued jobs awaiting specific servers. This paper introduces the Job Acceptance Multi-Server JAMS, a mechanism in which multiple CBS instances share a common job queue, enabling flexible job dispatching for parallel workloads. JAMS incorporates a job dismissal mechanism to address overloads, ensuring that only jobs with guaranteed resource availability are accepted. Each CBS instance checks if it can complete a job by its deadline, given probabilistic knowledge on its execution times, dismissing unfeasible jobs to avoid excessive tardiness across queued tasks. Implemented in Linux, JAMS  is evaluated with computation times drawn from an MPC task and synthetic datasets. The extensive experimental results we provide, demonstrate that JAMS effectively controls the deadline miss rate, maintaining it below a specified design threshold.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2025
Series
IEEE Real-Time and Embedded Technology and Applications Symposium, ISSN 2642-7346
Keywords
probabilistic scheduling, job dismissal
National Category
Computer Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-70438 (URN)10.1109/RTAS65571.2025.00009 (DOI)001543539900003 ()2-s2.0-105008056925 (Scopus ID)979-8-3315-4340-2 (ISBN)
Conference
2025 IEEE 31st Real-Time and Embedded Technology and Applications Symposium (RTAS),Irvine, CA, USA, 6-9 May 2025
Available from: 2025-03-17 Created: 2025-03-17 Last updated: 2026-02-16Bibliographically approved
Bujosa Mateu, D., Papadopoulos, A., Nolte, T., Ashjaei, S. M. & Proenza, J. (2025). Reducing Pessimism in Response Time Analysis ofAVB Traffic in TSN. Västerås
Open this publication in new window or tab >>Reducing Pessimism in Response Time Analysis ofAVB Traffic in TSN
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2025 (English)Report (Other academic)
Abstract [en]

Time-Sensitive Networking (TSN) is a set of standards with significant industrial impact potential, primarily due to its ability to integrate multiple traffic types with different requirements, offering great network flexibility. Among these traffic types, Audio-Video Bridging (AVB) stands out for its real-time guarantees and dynamic scheduling. In order to guarantee a specific set of AVB frames meet their timing requirements a Worst-Case Response Time Analysis (WCRTA) is essential. Unfortunately, current WCRTAs are often overly conservative, failing to guarantee schedulability for TSN systems operating even under low bandwidth conditions. This limits the practical usefulness of these analyses. Since TSN utilizes a multi-hop architecture, most WCRTAs analyze each link independently and then add the contributions. This compartmental analysis introduces pessimism, particularly when calculating the interference caused by other AVB frames with the same priority as the frame under analysis. In this paper, we address this issue by refining the Same-Priority Interference (SPI) calculation, leading to a significant improvement in the schedulability of WCRTAs and, consequently, the overall efficiency of TSN networks.

Place, publisher, year, edition, pages
Västerås: , 2025
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-69266 (URN)MDH-MRTC-353/2025-1-SE (ISRN)
Available from: 2024-12-04 Created: 2024-12-04 Last updated: 2025-10-10Bibliographically approved
Friebe, A., Marchetti-Spaccamela, A., Cucinotta, T., Papadopoulos, A., Nolte, T. & Baruah, S. (2025). Resource Management For Stochastic Parallel Synchronous Tasks: Bandits To The Rescue. Real-time systems, 61(3-4), 359-402
Open this publication in new window or tab >>Resource Management For Stochastic Parallel Synchronous Tasks: Bandits To The Rescue
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2025 (English)In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 61, no 3-4, p. 359-402Article in journal (Other academic) Published
Abstract [en]

In scheduling real-time tasks, we face the challenge of meeting hard deadlines while optimizing for some other objective, such as minimizing energy consumption. Formulating the optimization as a Multi-Armed Bandit (MAB) problem allows us to use MAB strategies to balance the exploitation of good choices based on observed data with the exploration of potentially better options.In this paper, we integrate hard real-time constraints with MAB strategies for resource management of a Stochastic Parallel Synchronous Task. On a platform with M cores available for the task, m<=M cores are initially assigned. Prior work has shown how to compute a virtual deadline such that assigning all M cores to the task if it has not completed by this virtual deadline guarantees that the deadline will be met. An MAB strategy is used to select the value of m. A Dynamic Power Management (DPM) energy model considering CPU sockets and sleep states is described. Experimental evaluation shows that MAB strategies learn consistently suitable m, and perform well compared to binary exponential search and greedy methods.

Place, publisher, year, edition, pages
Springer Nature, 2025
Keywords
Multicore scheduling, Multi-Armed Bandit, DAG task, Parallel Synchronous Task
National Category
Computer Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-70442 (URN)10.1007/s11241-025-09454-8 (DOI)001539464600001 ()2-s2.0-105010693032 (Scopus ID)
Available from: 2025-03-18 Created: 2025-03-18 Last updated: 2026-02-09Bibliographically approved
Lager, A., Miloradović, B., Spampinato, G., Nolte, T. & Papadopoulos, A. (2025). Stochastic Scheduling for Human-Robot Collaboration in Dynamic Manufacturing Environments. In: 34th IEEE International Conference on Robot and Human Interactive Communication (RO-MAN): . Paper presented at 34th IEEE International Conference on Robot and Human Interactive Communication (RO-MAN), Eindhoven, August 25-29, 2025.. Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Stochastic Scheduling for Human-Robot Collaboration in Dynamic Manufacturing Environments
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2025 (English)In: 34th IEEE International Conference on Robot and Human Interactive Communication (RO-MAN), Institute of Electrical and Electronics Engineers (IEEE) , 2025Conference paper, Published paper (Refereed)
Abstract [en]

Collaborative human-robot teams enhance efficiency and adaptability in manufacturing, but task scheduling in mixed-agent systems remains challenging due to the uncertainty of task execution times and the need for synchronization of agent actions. Existing task allocation models often rely on deterministic assumptions, limiting their effectiveness in dynamic environments. We propose a stochastic scheduling framework that models uncertainty through probabilistic makespan estimates, using convolutions and stochastic max operators for realistic performance evaluation. Our approach employs meta-heuristic optimization to generate executable schedules aligned with human preferences and system constraints. It features a novel deadlock detection and repair mechanism to manage cross-schedule dependencies and prevent execution failures. This framework offers a robust, scalable solution for real-world human-robot scheduling in uncertain, interdependent task environments.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2025
Series
IEEE International Workshop on Robot and Human Communication, RO-MAN, ISSN 1944-9445
National Category
Robotics and automation
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-73158 (URN)10.1109/RO-MAN63969.2025.11217642 (DOI)001672967200290 ()2-s2.0-105024560911 (Scopus ID)9798331587710 (ISBN)9798331587710 (ISBN)
Conference
34th IEEE International Conference on Robot and Human Interactive Communication (RO-MAN), Eindhoven, August 25-29, 2025.
Available from: 2025-09-02 Created: 2025-09-02 Last updated: 2026-03-04Bibliographically approved
Vitucci, C., Westerback, T., Sundmark, D., Forsberg, H., Nolte, T. & Jägemar, M. (2024). A Deductive Fault Analysis Method Based on Hypergraphs. In: IFAC-PapersOnLine: . Paper presented at 12th IFAC Symposium on Fault Detection, Supervision and Safety for Technical Processes SAFEPROCESS 2024: Ferrara, Italy, June 4 – 7, 2024 (pp. 378-383). Elsevier B.V. (4)
Open this publication in new window or tab >>A Deductive Fault Analysis Method Based on Hypergraphs
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2024 (English)In: IFAC-PapersOnLine, Elsevier B.V. , 2024, no 4, p. 378-383Conference paper, Published paper (Refereed)
Abstract [en]

Fault tree analysis is a system malfunction hazard evaluation quantitative and qualitative procedure. The method is well-known and widely used, especially in the safety systems domain, where it is a mandatory integral part of the so-called "Hazard Evaluation"documentation. This paper proposes an alternative or complementary deductive fault analysis method: it uses system topology to build a hypergraph representation of the system to identify component criticality and support loss of functionality probability evaluation. Once automated, the proposed method seems promising when the system engineers explore the different architectures. They may have indication about architecture's reliability without continuous feedback from the system safety team. The system safety team must check the solution once the engineers select the final architecture. They can also use the proposed method to validate the correctness of the fault tree analysis.

Place, publisher, year, edition, pages
Elsevier B.V., 2024
Series
IFAC-PapersOnLine, ISSN 2405-8963
Keywords
cut set level, fault analysis, hypergraph, loss of function probability, Accident prevention, Hazards, Reliability analysis, Trees (mathematics), Cut sets, Fault analysis methods, Fault tree analyses (FTA), Hazard evaluation, Hyper graph, System domain, System safety, Fault tree analysis
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:mdh:diva-68416 (URN)10.1016/j.ifacol.2024.07.247 (DOI)001296047100064 ()2-s2.0-85202861493 (Scopus ID)
Conference
12th IFAC Symposium on Fault Detection, Supervision and Safety for Technical Processes SAFEPROCESS 2024: Ferrara, Italy, June 4 – 7, 2024
Available from: 2024-09-11 Created: 2024-09-11 Last updated: 2025-10-10Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0001-6132-7945

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