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This paper presents a single monolithic wide band VCO for multi-standard radios. Analysis on a differential switched capacitor circuit is performed. Its impact on phase noise and power dissipation is especially addressed. The analysis is demonstrated and verified in a fully integrated CMOS VCO that consumes 2.7 mA from a 1.8 V supply and operates with a wide frequency band from 3.5 - 5.3 GHz. The measured phase noise is less than -110 dBc/Hz at 1 MHz offset within the entire tuning range.

A dual-band CMOS VCO with a divide-by-two circuit, operating between 4.7-6.2/2.35-3.1 GHz is demonstrated in a 0.35mum process. The VCO phase noise is reduced by matching the transconductance and impedance of the active devices. By using a divide-by-two stage quadrature signals for the 802.11 b/g standards are obtained. The VCO is optimized for low phase noise and small amplitude variations across the tuning range. The phase noise levels are less than -116.5 and -126 dBc/Hz at 1 MHz offset in the upper and lower frequency band respectively.

An improved high-performance dynamic-logic tri-state phase-frequency detector architecture is derived through extensive time domain analysis. In particular, the impact of the reset time's on the maximum operating frequency and phase characteristics of the phase-frequency detector is discussed. The analysis is verified for the presented improved architecture and excellent agreement between theory and simulation is observed. The phase-frequency detector architecture is proven to function for supply voltages below 1 V and has an increased frequency capability of more than 20% with a power consumption of 10 μW at 500 MHz input frequency.

A 3.5-5.3 GHz, low phase noise CMOS VCO with switched tuning for multi-standard radios is presented in this paper. Design of low phase noise and small amplitude variations across the operating frequency is shown to be important aspects in wide-band VCOs. An analytic expression for the output amplitude of the VCO is derived as a function of the switched capacitor resonator Q. The linear-time variant model was used for prediction of the phase noise and for deciding a proper tank current to achieve the minimum phase noise and amplitude variations across the frequency range. The results are verified in a fully integrated 0.18μm VCO with measured phase noise levels of less than -115 dBc/Hz at 1 MHz offset from the carrier while dissipating 6 mW of power. 

A fully integrated reconfigurable 3.6-6.0 GHz 0.18μm CMOS VCO with an automatic amplitude controller (AAC) for multi-standard front-ends is proposed. Due to the wide tuning range, utilizing mixed tuning technique, large amplitude variations over the band are observed. Thus a novel low noise AAC is implemented to stabilize the amplitude regardless of operation frequency. Measurements are performed both with and without the AAC loop active, showing that the AAC loops noise contributions are very small. The circuit displays phase noise levels of-124 dBc/Hz or less at 3 MHz offset within the entire frequency band while consuming 7.7-12.2 mW of power. The relative amplitude variation over the frequency band are 100 mV.

A low phase noise CMOS LC quadrature VCO (QVCO) with a wide frequency range of 3.6-5.6 GHz, designed in a standard 0.18 μm process for multi-standard front-ends, is presented. A significant advantage of the topology is the larger oscillation amplitude when compared to other conventional QVCO structures. The QVCO is compared to a double cross-coupled LC-tank differential oscillator, both in theory and experiments, for evaluation of its phase noise, providing a good insight into its performance. The measured data displays up to 2 dBc/Hz lower phase noise in the 1/f2 region for the QVCO, when consuming twice the current of the differential VCO, based on an identical LC-tank. Experimental results on the QVCO show a phase noise level of -127.5 dBc/Hz at 3 MHz offset from a 5.6 GHz carrier while dissipating 8 mA of current, resulting in a figure of merit of 181.3 dBc/Hz.

This paper presents a low-phase-noise differential bipolar Colpitts VCO, implemented in a 0.35μm BiCMOS process. A time-variant phase noise analysis yields closed-form symbolic expressions for the dominant noise sources in the I/f² phase-noise region. Measurements show a phase noise of -123 dBc/Hz at 1 MHz offset from a 2.8-3.1 GHz carrier, for a figure-of-merit of 183 dBc/Hz. A very good agreement between the derived theoretical formulas, spectreRF simulations, and measurements is observed.

The phase-noise theory and design of a differential CMOS LC-tank VCO with double switch pair is presented. A formula for the minimum achievable phase noise in the 1/f2 region is derived. The 2.15 to 2.35GHz 0.3μm CMOS VCO has a phase noise of -143.9dBc/Hz at 3MHz offset and draws 4mA from a 2.5V supply.

A novel CMOS high speed divide-by-two circuit with very low power consumption is proposed in this paper. The circuit features very low input capacitance and a wide locking range of 1.5-18 GHz with a power consumption of less than 13 mW at 1.8 V. The input sensitivity of the stage is improved significantly when compared to conventional dynamic loaded high frequency dividers. The concept and design issue of the circuit is presented together with a performance comparison to existing topologies. The idea is demonstrated and verified in a standard 0.18 μm CMOS process through realistic simulations originating from a complete layout using moderately extracted parasitics.

This paper presents a study of phase noise in CMOS Colpitts and LC-tank oscillators. Closed-form symbolic formulas for the 1/f² phase-noiseregion are derived for both the Colpitts oscillator (either single-ended or differential) and the LC-tank oscillator, yielding highly accurate results under very general assumptions. A comparison between the differential Colpitts and the LC-tank oscillator is also carried out, which shows that the latter is capable of a 2-dB lower phase-noise flgure-of-merit (FoM) when simplified oscillator designs and ideal MOS models are adopted. Several prototypesof both Colpitts and LC-tank oscillators have been implemented in a 0.35-μm CMOS process. The best performance of the LC-tank oscillatorsshows a phase noise of - 142 dBc/Hz at 3-MHz offset frequency from a 2.9-GHz carrier with a 16-mW power consumption, resulting in an excellent FoM of ∼189 dBc/Hz. For the same oscillation frequency, the FoM displayed by the differential Colpitts oscillators is ∼5 dB lower.