CAMP: a hierarchical cache architecture for multi-core mixed criticality processorsShow others and affiliations
2024 (English)In: International Journal of Parallel, Emergent and Distributed Systems, ISSN 1744-5760, E-ISSN 1744-5779, Vol. 39, no 3, p. 317-352Article in journal (Refereed) Published
Abstract [en]
CAMP proposes a hierarchical cache subsystem for multi-core mixed criticality processors, focusing on ensuring worst-case execution time (WCET) predictability in automotive applications. It incorporates criticality-aware locked L1 and L2 caches, reconfigurable at mode change intervals, along with criticality-aware last level cache partitioning. Evaluation using CACOSIM, Moola Multicore simulator, and CACTI simulation tools confirms the suitability of CAMP for keeping high-criticality jobs within timing budgets. A practical case study involving an automotive wake-up controller using the sniper v7.2 architecture simulator further validates its usability in real-world mixed criticality applications. CAMP presents a promising cache architecture for optimized multi-core mixed criticality systems.
Place, publisher, year, edition, pages
Informa UK Limited , 2024. Vol. 39, no 3, p. 317-352
Keywords [en]
cache coherence protocol, cache locking, cache partitioning, hierarchical cache architecture, Mixed-criticality systems, worst-case execution time (WCET), Architecture, Budget control, Cache memory, Computer architecture, Criticality (nuclear fission), Locks (fasteners), Network architecture, Bad-case execution time, Cache architecture, Cache coherence protocols, Hierarchical caches, Multi-cores, Worst-case execution time, Hierarchical systems
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:mdh:diva-65238DOI: 10.1080/17445760.2023.2293913ISI: 001130218200001Scopus ID: 2-s2.0-85180256653OAI: oai:DiVA.org:mdh-65238DiVA, id: diva2:1824003
2024-01-032024-01-032025-10-10Bibliographically approved