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FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs
University of Zanjan, Zanjan, Iran.
Tallinn University of Technology, Tallinn, Estonia.
University of Zanjan, Zanjan, Iran.
University of Zanjan, Zanjan, Iran.
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2024 (English)In: Proceedings of the Asian Test Symposium, Institute of Electrical and Electronics Engineers (IEEE) , 2024Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents FORTUNE, a hardware-agnostic fault tolerance technique for DNNs that leverages quantization to enhance reliability without significant performance overhead. Unlike conventional methods like Triple Modular Redundancy (TMR), which are computationally expensive, the proposed approach uses memory savings from quantization to protect the critical Most Significant Bit, improving fault tolerance in Deep Neural Networks (DNNs). Memory utilization has been reduced by 37.5% across all networks, with vulnerability in AlexNet reduced by 56% compared to the 8-bit version and 84% compared to the unprotected 3-bit version. These improvements come with only a minor increase in execution time of less than 3%. Using AlexNet as an example demonstrates how our approach effectively enhances memory utilization and resilience while causing only a minimal increase in execution time. 

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2024.
Series
Proceedings Asian Test Symposium, ISSN 2377-5386
Keywords [en]
deep neural networks, DNN accelerator, memory overhead, parallel processing, reliability, Fault tolerance, Parallel processing systems, Redundancy, Conventional methods, Deep neural network accelerator, Fault tolerance techniques, Memory overheads, Memory utilization, Neural-networks, Performance, Quantisation
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:mdh:diva-70998DOI: 10.1109/ATS64447.2024.10915463ISI: 001480998100043Scopus ID: 2-s2.0-105001127610ISBN: 9798331529161 (print)OAI: oai:DiVA.org:mdh-70998DiVA, id: diva2:1950944
Conference
33rd IEEE Asian Test Symposium, ATS 2024, Ahmedabad, 17 December 2024 through 20 December 2024
Available from: 2025-04-09 Created: 2025-04-09 Last updated: 2026-02-16Bibliographically approved

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Daneshtalab, Masoud

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